Method and system for power node current waveform modeling

ABSTRACT

A method and system for power node current waveform modeling provides improved accuracy for logic gate and functional block power node current models in computer-based verification and design tools. An output voltage waveform is generated, with each point a linear function of a set of input values corresponding to times at which the output voltage reaches predetermined fractions of the supply voltage. A set of coefficients is used for each point, as each output voltage has a different linear dependency on the input values. The output voltage waveform model is differentiated and multiplied by an effective load capacitance to determine an output current waveform. The method and system retain compatibility with existing software by using input values already present in the digital simulation models (e.g., delay times) that yield a subset of output voltage points. The coefficients of the model are predetermined for a circuit from principle components analysis.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to systems for modeling thebehavior of integrated circuits such as verifiers, simulators and designtools, and more particularly to a computer program that includesmodeling of digital integrated circuit power supply pin currentwaveforms.

2. Description of Related Art

Design tools and verification tools are necessary for modelinglarge-scale digital integrated circuits such as Very Large ScaleIntegration (VLSI) circuits. Millions of transistors and logic gates areoften combined on a single die and the performance of the die is modeledusing software that models the performance of the overall die based onknown (modeled) performance of individual gates, inverter/buffer modelsof gates, or models of larger functional blocks.

Power supply current for individual gates or blocks combines to generatethe power requirements for the overall die, and will typically combinein sub-groups to several power and ground pins that are connectedexternal to the integrated circuit package. The power supply pinconnections are typically inductive, while the external power suppliesto which the power pins connect are typically capacitive loads. Theinductive pin characteristic leads to voltage noise as the changingpower supply currents generate voltage drops across the pin inductances.Therefore, knowledge of power supply currents at power nodes of logicgates or larger functional blocks is valuable for knowing overallcurrent consumption and time-dependent behavior and for induced/radiatednoise modeling.

Present techniques for power supply node current modeling typicallycalculate power node current based upon a linear (ramp) model of inputand output voltages. Since the predominant (typically >90%) component ofpower node current derives from output capacitance charging anddischarging, the typical power node current model calculates the powernode current as the output load capacitance times the slope of theoutput voltage waveform, which is further typically simplified as arisetime/load capacitance product. The linear output voltage ramp thusyields a step (pulse) current component in the model, although providinga useful approximation, is inaccurate in modeling power supply behaviorand is generally unsuitable for noise analysis. Further, as power supplyvoltages are decreased (which is the trend for high-density integratedcircuits to reduce power dissipation and noise), the linear inputvoltage risetime model is increasingly inaccurate.

While more accurate models may be produced using more detailed analogcircuit analysis or waveshape fitting, the memory requirements andprocessing time are prohibitive for modeling large-scale circuits.Further, the analog and waveshape models are not directly compatiblewith existing power pin current models and logic gate models.

Therefore, it is desirable to implement an improved power node currentwaveform modeling algorithm. It would further be desirable to provide analgorithm that is compatible with existing power supply pin current andlogic gate models.

SUMMARY OF THE INVENTION

The objective of providing an improved power node current waveformmodeling algorithm is achieved in a method for modeling characteristicsof a logical circuit block. The method generates an output voltagewaveform of the logical circuit block by using a linear model thatcalculates points of the waveform from known points received as inputs.The inputs to the method are time values at which the output voltagereaches predetermined fractions of an input voltage signal. The timevalues are multiplied by coefficients from a set of coefficients foreach output waveform point that are determined from a statistical modelof logical circuit block behavior, yielding an output voltage waveform.The calculated output voltage waveform can then be differentiated andmultiplied by a predetermined load capacitance to yield an outputcurrent waveform. The method retains compatibility with present timingsimulators, as the delay time (taken as the 50% voltage point) and therise time (which yields a difference of the 70% and 30% voltage pointsor other pair of voltage points) can be used to provide the input timevalues.

The invention may further be embodied in a workstation computerexecuting program instructions for carrying out the steps of the method,and in a computer program product having a storage media for thoseprogram instructions.

The foregoing and other objectives, features, and advantages of theinvention will be apparent from the following, more particular,description of the preferred embodiment of the invention, as illustratedin the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a pictorial diagram of a workstation computer system in whichmethods in accordance with an embodiment of the present invention areperformed.

FIG. 2A is a block diagram of a logical circuit block representation inaccordance with methods embodying the present invention.

FIGS. 2B-2D are graphs depicting voltage and current waveforms withinthe logical circuit block of FIG. 2A.

FIG. 3 is a flow chart depicting a method in accordance with anembodiment of the present invention.

FIG. 4 is a pictorial diagram depicting the flow of a method inaccordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

Referring to the figures, and particularly to FIG. 1, a workstationcomputer system, in which methods according to an embodiment of thepresent invention are performed, is depicted. A workstation computer 12,having a processor 16 coupled to a memory 17, for executing programinstructions from memory 17, wherein the program instructions includeprogram instructions for executing one or more methods in accordancewith an embodiment of the present invention.

Workstation computer 12 is coupled to a graphical display 13 fordisplaying program output such as simulation results and circuitstructure input and verification programs implementing embodiments ofthe present invention. Workstation computer 12 is further coupled toinput devices such as a mouse 15 and a keyboard 14 for receiving userinput. Workstation computer may be coupled to a public network such asthe Internet, or may be a private network such as the various“intra-nets” and software containing program instructions embodyingmethods in accordance with embodiments of the present invention may belocated on remote computers or locally within workstation computer 12.

Referring now to FIG. 2A, a block diagram of a simplified integratedcircuit 20 for illustrating the models of the present invention isshown. Logical circuit blocks 21A, 21B and 21C may be gates,inverters/buffers or larger digital functional blocks. FIG. 2B depicts asimulated voltage waveform 23 for logical circuit block 21A usingexisting simulation algorithms. To simulate the output current requiredwhen logical circuit block 21A changes its output value, the effectiveload capacitance C_(L) may be multiplied by the derivative of thevoltage waveform shown in graph 23, but that would yield a constantcurrent due to the linear rise of V_(o), yielding inaccurate results. Anactual output voltage waveform 24 and current waveform 25 are shown inFIGS. 2C and 2D respectively, to depict the differences between linearvoltage/pulse current models as implemented in typical simulationsoftware and the actual shapes of power supply node current 25 and logicoutput voltage waveforms 24 for logic block 21A within integratedcircuit 20.

The power supply current I_(D1) for an individual block 21A may beaccurately calculated from load capacitance C_(L) and the output voltagewaveform at node B, as cross-conduction and other sources of internalgate dissipation are generally insignificant compared to the currentrequired to drive the output load (which includes generally one or moretransistor gates in addition to circuit path capacitance). In order tomodel the current waveform at an external pin of integrated circuit 20such as V_(dd1), current may be modeled for each of the power nodes ofthe logical circuit blocks (21A, 21B and any other blocks connected topin V_(dd1)), and summed together to achieve an overall currentwaveform.

In order to accurately model current I_(D1) (and consequently the powerpin V_(dd1), V_(dd2), V_(ss1), and V_(ss2) current once all logic blockpower node currents are modeled), an accurate model of the outputvoltage waveforms of each of the logical circuit blocks are needed.However, typical simulation software only calculates a rise time anddelay for each logical circuit block. The present invention provides amethod for using the rise time and delay to generate a highly accuratemodel of a logic block output voltage waveform. The output voltagewaveform is differentiated, either by calculating the slope of the linesbetween points of the calculated waveform (linear method) or using ahigher order derivative approximation technique.

Referring now to FIG. 3, a method in accordance with an embodiment ofthe present invention is depicted in a flowchart. First the logicalcircuit block is simulated in an analog fashion (using SPICE or anotheranalysis tool) to produce output waveforms (step 30) over various inputwaveform and circuit conditions, such as power supply voltage, inputvoltage rise time and input voltage swing. After a large number ofwaveforms have been generated, a statistical model is used to computecoefficients relating a subset of output waveform time/voltage fractionpoints (i.e., the points in time at which the output waveform voltagereaches a particular fraction of the power supply voltage) to the otherpoints in the output voltage waveform (step 31). Steps 30 and 32 needonly be performed for a given logical circuit block once. The linearcoefficients are then retained for subsequent generation of the outputvoltage waveform in circuit timing simulation.

During timing simulation, an input set of output voltage waveformtime/value fraction values (i.e., points in time at which the outputvoltage waveform have reached predetermined fractions of the supplyvoltage) are received (step 32). The input values received may be thedelay time and rise time of the logic block, as the delay time is thetime when the output voltage reaches half of the supply voltage and therise time is the difference between the time that the output voltagereaches 70% of supply voltage and the time that the output voltagereaches 30% of the supply voltage. Another pair of voltage points suchas the 20% and 80% or 10% and 90% points may be used to determine therise time input, and the method of the present invention is notrestricted to the use of delay and rise time, but may use any calculatedvoltage points to calculate the other points in the waveform using thestatistically-derived coefficients.

The output voltage waveform is computed by multiplying the delay timeand rise time by the linear coefficients determined in steps 30 and 31and summing the resulting terms for each output voltage waveform point(step 33). After all of the output waveform points are generated(decision 34), the output waveform is differentiated and multiplied byan effective load capacitance to produce an output current waveform(step 35). If the integrated circuit pin currents are being modeled,waveforms generated for each of the logical circuit blocks having powernodes connected to the pin are summed to produce a current waveform forthe pin (step 36).

Referring now to FIG. 4, a flow diagram depicting generation of themodel of present invention is shown. First, the output voltage waveformis modeled as a set of discrete points in time for which the outputvoltage waveform reaches predetermined fractions of the supply voltage.As an example, a 20 point waveform model is used in herein (e.g., 0-100%in 5% steps) numbered from 0 to 19 and indices mentioned refer to thevoltage/time pairs in the 20 point sequence. Therefore, the 50% voltagepoint is taken as index 11 and the 30% and 70% points are taken asindices 5 and 15, respectively. The above-chosen voltage/time pairspermit direct use of the 50% delay time and 30%-70% rise time as inputto the output voltage waveform model.

Next, a matrix of the time points is generated to calculate the othertime points. Naturally, the identity matrix will yield the exact timepoints, since each point in the waveform would be used to calculateitself with a coefficient of unity. However, the objective is to reducethe number of input points required to construct a model of the outputwaveform, in particular to reduce the model to require as input only thedelay and rise time predicted voltage points. The matrix is factored toinclude only A_(i,11) (the 50% delay time coefficients) and A_(i,5),A_(i,15) where B=A_(i,15)=−A_(i,5), yielding a model that can calculateall of the waveform points from the delay time t₁₁ and the rise timet₁₅−t₅ (Since the contributions from t₅A_(i,5)+t₁₅A_(i,15) reduce underthe constraint to B(t₁₅−t₅). It should be noted, that while the model isa linear model using linear equations to calculate the output voltagewaveform, the coefficients are unique to each output waveform voltagepoint and therefore is not modeling the output waveform as a straightline or multi-slope line, but as a complex relationship between theknown input points and each output point.

The process of reducing the number of factors to model the entire matrixis a process known as “factoring” and a method that may be used togenerate the values for the coefficients is “principle componentsanalysis” which many commercial statistical software packages support.Principle components analysis determines coefficients for selectedfactors by maximizing the variance of the selected factors whileminimizing the variance of the other points. The varianceminimization/maximization produces coefficients that will generate theother points in the matrix with minimal deviation generated byvariations in the input values, which correspond to known elements andare not calculated in the model. Therefore, no matter what the variancein the input values, the other values computed to complete the waveformmodel will have minimal dependence on any deviations in the inputvalues.

A correlation check was used to verify the accuracy of the model, aswell as error plots and “scree” diagrams that show the model error as afunction of the number of selected input values. For an exemplarymodeling of the present invention, the correlation coefficients havebeen shown to be not less than 0.999 for each linear equation, with apeak-to-peak error of less than 20% over all of the modeled circuit andinput conditions. The error generated by the model for two inputvariables yielded an unexplained error level of 0.05%, showing that twovariables (rise time and delay time) are sufficient to generate theoutput voltage waveform without introducing significant error due to themodel.

While the invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in form,and details may be made therein without departing from the spirit andscope of the invention.

What is claimed is:
 1. A method for modeling characteristics of alogical circuit block, comprising: receiving input of a first pluralityof values corresponding to times at which an output voltage of saidlogical circuit block reaches selected predetermined fractions of asupply voltage; and generating a second time value for which said outputvoltage reaches a different predetermined fraction of said supplyvoltage by multiplying each of said plurality of values by acorresponding one of a set of coefficients that statistically relatesaid first plurality of input values to said second time value, andsumming the multiplied values to produce a resulting time at which saidoutput voltage reaches said different predetermined fraction of saidsupply voltage.
 2. The method of claim 1, further comprising repeatingsaid generating to generate a second plurality of time values at whichsaid output voltage reaches other predetermined fractions of said supplyvoltage, whereby a waveform representing an output voltage of saidlogical circuit block is generated.
 3. The method of claim 2, furthercomprising: differentiating said output voltage waveform representation;and multiplying a result of said differentiating by an effective loadcapacitance to produce current values representing an output currentwaveform.
 4. The method of claim 3, wherein said receiving, generating,differentiating, and multiplying are repeated for multiple logicalcircuit blocks resulting in a plurality of output current waveforms andfurther comprising summing said output current waveforms to provide apin current for an integrated circuit package containing said logicalcircuit blocks.
 5. The method of claim 2, wherein said first pluralityof input values comprises a third time value corresponding to a supplyvoltage fraction of 0.3, a fourth time value corresponding to a supplyvoltage fraction of 0.5 and a fifth time value corresponding to a supplyvoltage fraction of 0.7, and wherein said coefficient corresponding tosaid third time value and said coefficient corresponding to said fifthtime value are equal in magnitude and opposite in sign, whereby saidgenerating may be performed in conformity with a delay time and a risetime of said logical circuit block.
 6. The method of claim 2, whereinsaid first plurality of input values comprises a third time valuecorresponding to a supply voltage fraction of 0.5, a fourth time valuecorresponding to another supply voltage fraction less than 0.5 by apredetermined amount, and a fifth time value corresponding to a supplyvoltage fraction greater than 0.5 by said predetermined amount, andwherein said coefficient corresponding to said fourth time value andsaid fifth time value are equal in magnitude and opposite in sign,whereby said generating may be performed in conformity with a delay timeand a rise time of said logical circuit block.
 7. The method of claim 1,wherein said first plurality of input values comprises a third timevalue corresponding to a supply voltage fraction of 0.3, a fourth timevalue corresponding to a supply voltage fraction of 0.5 and a fifth timevalue corresponding to a supply voltage fraction of 0.7, and whereinsaid coefficient corresponding to said third time value and saidcoefficient corresponding to said fifth time value are equal inmagnitude and opposite in sign, whereby said generating may be performedin conformity with a delay time and a rise time of said logical circuitblock.
 8. The method of claim 1, further comprising: simulating saidlogical circuit block over a variety of input waveforms and circuitconditions to produce a plurality of output voltage waveforms for saidlogical circuit block; and determining said set of coefficients eachrelating a time at which said output voltage waveform reaches saidselected predetermined fractions of said supply voltage to times atwhich said output voltage waveform reaches different predeterminedfractions of said supply voltage via a statistical reduction of saidplurality of output voltage waveforms that maximizes the variance oftimes at which said output voltage waveforms reach said selectedpredetermined fractions of said supply voltage and minimizes thevariance of other times at which said output voltage waveforms reachsaid different predetermined fractions of said output voltage.
 9. Acomputer program product for use with a workstation computer, whereinsaid computer program product comprises signal bearing media containingprogram instructions for execution within said workstation computer formodeling characteristics of a logical circuit block, wherein saidprogram instructions comprise program instructions for: receiving inputof a first plurality of input values corresponding to times at which anoutput voltage of said logical circuit block reaches selectedpredetermined fractions of a supply voltage; and generating a secondtime value for which said output voltage reaches a differentpredetermined fraction of said supply voltage by multiplying each ofsaid first plurality of input values by a corresponding one of a set ofcoefficients that statistically relate said first plurality of inputvalues to said second time value, and summing the multiplied values toproduce a resulting time at which said output voltage reaches saiddifferent predetermined fraction of said supply voltage.
 10. Thecomputer program product of claim 9, wherein said program instructionsfurther comprise program instructions for repeating said programinstructions for generating to generate a second plurality of timevalues at which said output voltage reaches other predeterminedfractions of said supply voltage, whereby a waveform representing anoutput voltage of said logical circuit block is generated.
 11. Thecomputer program product of claim 10, wherein said program instructionsfurther comprise program instructions for: differentiating said outputvoltage waveform representation; and multiplying a result of saiddifferentiating by an effective load capacitance to produce currentvalues representing an output current waveform.
 12. The computer programproduct of claim 11, wherein said program instructions further compriseprogram instructions for repeating said receiving, generating,differentiating, and multiplying for multiple logical circuit blocksresulting in a plurality of output current waveforms and furthercomprising program instructions for summing said output currentwaveforms to provide a pin current for an integrated circuit packagecontaining said logical circuit blocks.
 13. The computer program productof claim 10, wherein said plurality of input values comprises a thirdtime value corresponding to a supply voltage fraction of 0.3, a fourthtime value corresponding to a supply voltage fraction of 0.5 and a fifthtime value corresponding to a supply voltage fraction of 0.7, andwherein said coefficient corresponding to said third time value and saidcoefficient corresponding to said fifth time value are equal inmagnitude and opposite in sign, whereby said generating may be performedin conformity with a delay time and a rise time of said logical circuitblock.
 14. The computer program product of claim 10, wherein saidplurality of input values comprises a third time value corresponding toa supply voltage fraction of 0.5, a fourth time value corresponding toanother supply voltage fraction less than 0.5 by a predetermined amount,and a fifth time value corresponding to a supply voltage fractiongreater than 0.5 by said predetermined amount, and wherein saidcoefficient corresponding to said fourth time value and said fifth timevalue are equal in magnitude and opposite in sign, whereby saidgenerating may be performed in conformity with a delay time and a risetime of said logical circuit block.
 15. The computer program product ofclaim 9, wherein said plurality of input values comprises a third timevalue corresponding to a supply voltage fraction of 0.3, a fourth timevalue corresponding to a supply voltage fraction of 0.5 and a fifth timevalue corresponding to a supply voltage fraction of 0.7, and whereinsaid coefficient corresponding to said third time value and saidcoefficient corresponding to said fifth time value are equal inmagnitude and opposite in sign, whereby said generating may be performedin conformity with a delay time and a rise time of said logical circuitblock.
 16. The computer program product of claim 9, wherein said programinstructions further comprise program instructions for: simulating saidlogical circuit block over a variety of input waveforms and circuitconditions to produce a plurality of output voltage waveforms for saidlogical circuit block; and determining said set of coefficients eachrelating a time at which said output voltage waveform reaches saidselected predetermined fractions of said supply voltage to times atwhich said output voltage waveform reaches different predeterminedfractions of said supply voltage via a statistical reduction of saidplurality of output voltage waveforms that maximizes the variance oftimes at which said output voltage waveforms reach said selectedpredetermined fractions of said supply voltage and minimizes thevariance of other times at which said output voltage waveforms reachsaid different predetermined fractions of said output voltage.
 17. Aworkstation comprising: a memory for storing program instructions anddata values for modeling characteristics of a logical circuit block; aprocessor for executing said program instructions, wherein said programinstructions comprise program instructions for receiving input of afirst plurality of input values corresponding to times at which anoutput voltage of said logical circuit block reaches selectedpredetermined fractions of a supply voltage, and generating a secondtime value for which said output voltage reaches a differentpredetermined fraction of said supply voltage by multiplying each ofsaid first plurality of input values by a corresponding one of a set ofcoefficients that statistically relate said first plurality of inputvalues to said second time value, and summing the multiplied values toproduce a resulting time at which said output voltage reaches saiddifferent predetermined fraction of said supply voltage.
 18. Theworkstation of claim 17, wherein said program instructions forgenerating are repeated to generate a second plurality of time values atwhich said output voltage reaches other predetermined fractions of saidsupply voltage, whereby a waveform representing an output voltage ofsaid logical circuit block is generated.
 19. The workstation of claim18, wherein said program instructions further comprise programinstructions for: differentiating said output voltage waveformrepresentation; and multiplying a result of said differentiating by aneffective load capacitance to produce current values representing anoutput current waveform.
 20. The workstation of claim 19, wherein saidprogram instructions for receiving, generating, differentiating, andmultiplying are repeated for multiple logical circuit blocks resultingin a plurality of output current waveforms and further comprisingprogram instructions for summing said output current waveforms toprovide a pin current for an integrated circuit package containing saidlogical circuit blocks.
 21. The workstation of claim 18, wherein saidplurality of input values comprises a third time value corresponding toa supply voltage fraction of 0.3, a fourth time value corresponding to asupply voltage fraction of 0.5 and a fifth time value corresponding to asupply voltage fraction of 0.7, and wherein said coefficientcorresponding to said third time value and said coefficientcorresponding to said fifth time value are equal in magnitude andopposite in sign, whereby said generating may be performed in conformitywith a delay time and a rise time of said logical circuit block.
 22. Theworkstation of claim 18, wherein said plurality of input valuescomprises a third time value corresponding to a supply voltage fractionof 0.5, a fourth time value corresponding to another supply voltagefraction less than 0.5 by a predetermined amount, and a fifth time valuecorresponding to a supply voltage fraction greater than 0.5 by saidpredetermined amount, and wherein said coefficient corresponding to saidfourth time value and said fifth time value are equal in magnitude andopposite in sign, whereby said generating may be performed in conformitywith a delay time and a rise time of said logical circuit block.
 23. Theworkstation of claim 17, wherein said plurality of input valuescomprises a third time value corresponding to a supply voltage fractionof 0.3, a fourth time value corresponding to a supply voltage fractionof 0.5 and a fifth time value corresponding to a supply voltage fractionof 0.7, and wherein said coefficient corresponding to said third timevalue and said coefficient corresponding to said fifth time value areequal in magnitude and opposite in sign, whereby said generating may beperformed in conformity with a delay time and a rise time of saidlogical circuit block.
 24. The workstation of claim 17, wherein saidprogram instructions further comprise program instructions for:simulating said logical circuit block over a variety of input waveformsand circuit conditions to produce a plurality of output voltagewaveforms for said logical circuit block; and determining said-set ofcoefficients each relating a time at which said output voltage waveformreaches said selected predetermined fractions of said supply voltage totimes at which said output voltage waveform reaches differentpredetermined fractions of said supply voltage via a statisticalreduction of said plurality of output voltage waveforms that maximizesthe variance of times at which said output voltage waveforms reach saidselected predetermined fractions of said supply voltage and minimizesthe variance of other times at which said output voltage waveforms reachsaid different predetermined fractions of said output voltage.